View DSP56857_2843402.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

56800e 16-bit digital signal controllers freescale.com 56857 data sheet technical data DSP56857 rev. 6 01/2007

56857 technical data, rev. 6 freescale semiconductor 3 56857 block diagram jtag/ enhanced once program controller and hardware looping unit data alu 16 x 16 + 36 ? 36-bit mac three 16-bit input registers four 36-bit accumulators address generation unit bit manipulation unit 16-bit dsp56800e core xtal extal interrupt controller quad timer or gpiog 4 clko 4 reset irqa irqb v dd v ssio v dda v ssa cs0-cs3[3:0] modea-c or 6 program memory 40,960 x 16 sram boot rom 1024 x 16 rom data memory 24,576 x 16 sram pdb pdb xab1 xab2 xdb2 cdbr spi or gpiof 2 sci or gpioe ipbus bridge (ipbb) 3 (gpioh0-h2) 8 12 v ddio 12 decoding peripherals 4 system bus control memory pab pab cdbw cdbr cdbw v ss 5 6 essi0 or gpioc 6 essi1 or gpiod host interface or gpiob 16 rsto dma 6 channel por integration module system cop/ watch- dog time of day clock generator osc pll 2 ipbus clk cop/tod clk core clk used as gpioa0-a3 ipab ipwdb iprdb dma requests gpio contol 56857 general description ? 120 mips at 120mhz ? 40k x 16-bit program sram ? 24k x 16-bit data sram ? 1k x 16-bit boot rom ? six (6) independent channels of dma ? two (2) enhanced synchronous serial interfaces (essi) ? two (2) serial commun ication interfaces (sci) ? serial port interface (spi) ? four (4) dedicated gpio ? 8-bit parallel host interface ? general purpose 16-bit quad timer ? jtag/enhanced on-chip emulation (once?) for unobtrusive, real-time debugging ? computer operating properly (cop)/watchdog timer ? time-of-day (tod) ? 100 lqfp package ?up to 47 gpio
56857 technical data, rev. 6 4 freescale semiconductor part 1 overview 1.1 56857 features 1.1.1 digital signal processing core ? efficient 16-bit engine with dual harvard architecture ? 120 million instructions per second (mips) at 120m hz core frequency ? single-cycle 16 16-bit parallel multiplier-accumulator (mac) ? four (4) 36-bit accumulators including extension bits ? 16-bit bidirectional shifter ? parallel instruction set with unique dsp addressing modes ? hardware do and rep loops ? three (3) internal address buses ? four (4) internal data buses ? instruction set supports both dsp and controller functions ? four (4) hardware interrupt levels ? five (5) software interrupt levels ? controller-style addressing modes and instructions for compact code ? efficient c compiler and local variable support ? software subroutine and interrupt stac k with depth limited only by memory ? jtag/enhanced once debug programming interface 1.1.2 memory ? harvard architecture permits up to three (3 ) simultaneous accesses to program and data memory ?on-chip memory ?40k 16-bit program ram ?24k 16-bit data ram ?1k 16-bit boot rom ? chip select logic used as dedicated gpio 1.1.3 peripheral circuits for 56857 ? general purpose 16-bit quad timer* ?two serial communic ation interfaces (sci)* ? serial peripheral interface (spi) port* ? two (2) enhanced synchronous serial interface (essi) modules* ? computer operating properly (cop)/watchdog timer ? jtag/enhanced on-chip emulation (once) for unobtrusive, real-time debugging ? six (6) independent channels of dma
56857 description 56857 technical data, rev. 6 freescale semiconductor 5 ? 8-bit parallel host interface* ?time of day ?up to 47 gpio * each peripheral i/o can be used altern ately as a general purpose i/o if not needed 1.1.4 energy information ? fabricated in high-density cmos with 3.3v, ttl-compatible digital inputs ? wait and stop modes available 1.2 56857 description the 56857 is a member of the 56800e core -based family of controllers. it combines, on a single chip, the processing power of a digital signal processor (dsp) and the functionality of a microcontroller with a flexible set of peripherals to create an extrem ely cost-effective solution. because of its low cost, configuration flexibility, and comp act program code, the 56857 is well-s uited for many applications. the 56857 includes many peripherals that are especially usef ul for low-end internet appliance applications and low-end client applications su ch as telephony; portable devices; internet audio; and point-of-sale systems, such as noise suppression; id tag readers; sonic/subsonic de tectors; security access devices; remote metering; sonic alarms. the 56800e core is based on a harv ard-style architecture c onsisting of three execution units operating in parallel, allowing as many as six operations per instruction cycle. the microprocessor- style programming model and optimized instruction se t allow straightforward generation of efficient, compact dsp and control code. the instruction set is also highly effi cient for c compilers, en abling rapid development of optimized control applications. the 56857 supports program execution fr om either internal or external memories. two data operands can be accessed from the on- chip data ram per instruction cycl e. the 56857 also pr ovides two external dedicated interrupt lines, and up to 47 general purpose input/output (gpi o) lines, depending on peripheral configuration. the 56857 controller includes 40k wo rds of program ram, 24k words of data ram a nd 1k of boot rom. this controller also provides a full set of standard progr ammable peripherals that include 8-bit parallel host interface, two enhanced synchr onous serial interfaces (essi), one serial peripheral interface (spi), two serial communications interfaces (sci), and one quad timer. the essis, spi, scis io and quad timer can be used as general purpose input/outputs when its pr imary function is not required.
56857 technical data, rev. 6 6 freescale semiconductor 1.3 state of the art development environment ? processor expert tm (pe) provides a rapid application design (rad) tool that combines easy-to-use component-based software ap plication creation with an expert knowledge system. ? the code warrior integrated development environm ent is a sophisticated to ol for code navigation, compiling, and debugging. a complete set of eval uation modules (evms) and development system cards will support concurrent engineering. together, pe, code warrior and evms create a complete, scalable tools solution for easy, fast, and efficient development. 1.4 product documentation the four documents listed in table 1-1 are required for a complete desc ription of and proper design with the 56857. documentation is available from local fr eescale distributors, free scale semiconductor sales offices, freescale literature dist ribution centers, or online at www.freescale.com . 1.5 data sheet conventions this data sheet uses the following conventions: table 1-1 56857 chip documentation topic description order number 56800e reference manual detailed description of the 56800e architecture, 16-bit core processor and the instruction set 56800erm DSP56857 user?s manual detailed description of memory, peripherals, and interfaces of the 56857 dsp5685xum DSP56857 technical data sheet electrical and timing specifications, pin descriptions, and package descriptions (this document) DSP56857 DSP56857 errata details any chip issues that might be present DSP56857e overbar this is used to indicate a signal that is active when pulled low. for example, the reset pin is active when low. ?asserted? a high true (active high) signal is high or a low true (active low) signal is low. ?deasserted? a high true (active high) signal is low or a low true (active low) signal is high. examples: signal/symbol logic state signal state voltage 1 1. values for vil, vol, vih, and voh are defined by individual pr oduct specifications. pin true asserted v il /v ol pin false deasserted v ih /v oh pin true asserted v ih /v oh pin false deasserted v il /v ol
introduction 56857 technical data, rev. 6 freescale semiconductor 7 part 2 signal/connection descriptions 2.1 introduction the input and output signals of the 56857 are organized into fu nctional groups, as shown in table 2-1 and as illustrated in figure 2-1 . in table 3-1 each table row describes the pack age pin and the signal or signals present. 1. v dd = v dd core, v ss = v ss core, v ddio = v dd io, v ssio = v ss io, v dda = v dd ana, v ssa = v ss ana 2. mode a, mode b and mode c can be used as gpio after the bootstrap process has completed. 3. the following host interface si gnals are multiplexed: hrwb to hrd , hds to hwr , hreq to htrq and hack to hrrq. table 2-1 functional group pin allocations functional group number of pins power (v dd, v ddio, or v dda ) (8, 12, 1) 1 ground (v ss, v ssio, or v ssa ) (5, 12, 2) 1 pll and clock 3 chip select logic used as dedicated gpio 4 interrupt and program control 7 2 host interface (hi)* 16 3 enhanced synchronous serial interface (essi0) port* 6 enhanced synchronous serial interface (essi1) port* 6 serial communications interface (sci0) ports* 2 serial communications interface (sci1) ports* 2 serial peripheral in terface (spi) port* 4 quad timer module port* 4 jtag/enhanced on-chip emulation (eonce) 6 *alternately, gpio pins
56857 technical data, rev. 6 8 freescale semiconductor figure 2-1 56857 signals identi fied by functional group 2 1. specifically for pll, osc, and por. 2. alternate pin functions are shown in parentheses. 56857 logic power i/o power sci 0 jtag / enhanced once timer module essi 0 spi chip select analog power 1 pll / clock sci 2 essi 1 interrupt / program control v dd v ss v ddio v ssio v dda v ssa cs0 - cs3 (gpioa0 - a3) hd0 - hd7 (gpiob0 - b7) ha0 - ha2 (gpiob8 - b10) hrwb (hrd ) (gpiob11) hds (hwr ) (gpiob12) hcs (gpiob13) hreq (htrq ) (gpiob14) hack (hrrq) (gpiob15) tio0 - tio3 (gpiog0 - g3) irqa irqb mode a, mode b, mode c (gpioh0 - h2) reset rsto host interface xtal rxdo (gpioe0) txdo (gpioe1) rxd1 (gpioe2) txd1 (gpioe3) std0 (gpioc0) srd0 (gpioc1) sck0 (gpioc2) sc00 (gpioc3) sc01 (gpioc4) sc02 (gpioc5) miso (gpiof0) mosi (gpiof1) sck (gpiof2) ss (gpiof3) std1 (gpiod0) srd1 (gpiod1) sck1 (gpiod2) sc10 (gpiod3) sc11 (gpiod4) sc12 (gpiod5) extal clko tck tdi tdo tms trst de 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 1 1 4 1 1 1 1 1 3 8 4 2 1 12 12 5 8
introduction 56857 technical data, rev. 6 freescale semiconductor 9 part 3 signals and package information all digital inputs have a weak inte rnal pull-up circuit asso ciated with them. thes e pull-up circuits are enabled by default. exceptions: 1. when a pin has gpio functionality, the pull-up may be disabled under software control. 2. mode a, mode b, and mode c pins have no pull-up. 3. tck has a weak pull-down circuit always active. 4. bidirectional i/o pullups automatically disable when the output is enabled. this table is presented consistently with the signals identified by functional group figure. 1. bold entries in the type column represents the state of the pin just out of reset. 2. output(z) means an output in a high-z condition. table 3-1 56857 signal and packag e information for the 100-pin lqfp pin no. signal name type description 8v dd v dd power (v dd ) ?these pins provide power to the internal structures of the chip, and should all be attached to v dd. 25 v dd 36 v dd 50 v dd 59 v dd 60 v dd 76 v dd 87 v dd 9v ss v ss ground (v ss ) ?these pins provide grounding for the internal structures of the chip and should all be attached to v ss. 37 v ss 38 v ss 61 v ss 88 v ss
56857 technical data, rev. 6 10 freescale semiconductor 5v ddio v ddio power (v ddio ) ?these pins provide power for all i/o and esd structures of the chip, and should all be attached to v ddio (3.3v) . 6v ddio 13 v ddio 34 v ddio 45 v ddio 47 v ddio 48 v ddio v ddio power (v ddio ) ?these pins provide power for all i/o and esd structures of the chip, and should all be attached to v ddio (3.3v) . 53 v ddio 72 v ddio 80 v ddio 90 v ddio 98 v ddio 7v ssio v ssio ground (v ssio ) ?these pins provide grounding for all i/o and esd structures of the chip and should all be attached to v ss. 14 v ssio 35 v ssio 46 v ssio 49 v ssio 54 v ssio 73 v ssio 82 v ssio 89 v ssio 91 v ssio 99 v ssio 100 v ssio 17 v dda v dda analog power (v dda ) ?these pins supply an analog power source. table 3-1 56857 signal and package informat ion for the 100-pin lqfp (continued) pin no. signal name type description
introduction 56857 technical data, rev. 6 freescale semiconductor 11 18 v ssa v ssa analog ground (v ssa ) ?this pin supplies an analog ground. 19 v ssa 55 cs0 gpioa0 output input /output external chip select (cs0 ) ?this pin is used as a dedicated gpio. port a gpio (0) ?this pin is a general purpose i/o (gpio) pin when not configured for host port usage. 56 cs1 gpioa1 output input /output external chip select (cs1 ) ?this pin is used as a dedicated gpio . port a gpio (1) ?this pin is a general purpose i/o (gpio) pin when not configured for host port usage. 57 cs2 gpioa2 output input /output external chip select (cs2 ) ?this pin is used as a dedicated gpio. port a gpio (2) ?this pin is a general purpose i/o (gpio) pin when not configured for host port usage. 58 cs3 gpioa3 output input /output external chip select (cs3 ) ?this pin is used as a dedicated gpio . port a gpio (3) ?this pin is a general purpose i/o (gpio) pin when not configured for host port usage. 22 hd0 gpiob0 input input/output host address (hd0)? this input provides the address selection for hi registers. this pin is disconnected internally. port b gpio (0) ?this pin is a general purpose i/o (gpio) pin when not configured for host port usage. 23 hd1 gpiob1 input input/output host address (hd1)? this input provides the address selection for hi registers. this pin is disconnected internally. port b gpio (1) ?this pin is a general purpose i/o (gpio) pins when not configured for host port usage. 24 hd2 gpiob2 input input/output host address (hd2)? this input provides the address selection for hi registers. this pin is disconnected internally. port b gpio (2) ?this pin is a general purpose i/o (gpio) pins when not configured for host port usage. table 3-1 56857 signal and package informat ion for the 100-pin lqfp (continued) pin no. signal name type description
56857 technical data, rev. 6 12 freescale semiconductor 29 hd3 gpiob3 input input/output host address (hd3)? this input provides the address selection for hi registers. this pin is disconnected internally. port b gpio (3) ?this pin is a general purpose i/o (gpio) pins when not configured for host port usage. 30 hd4 gpiob4 input input/output host address (hd4)? this input provides the address selection for hi registers. this pin is disconnected internally. port b gpio (4) ?this pin is a general purpose i/o (gpio) pins when not configured for host port usage. 31 hd5 gpiob5 input input/output host address (hd5)? this input provides the address selection for hi registers. this pin is disconnected internally. port b gpio (5) ?this pin is a general purpose i/o (gpio) pins when not configured for host port usage. 32 hd6 gpiob6 input input/output host address (hd6)? this input provides the address selection for hi registers. this pin is disconnected internally. port b gpio (6) ?this pin is a general purpose i/o (gpio) pins when not configured for host port usage. 33 hd7 gpiob7 input input/output host address (hd7)? this input provides the address selection for hi registers. this pin is disconnected internally. port b gpio (7) ?this pin is a general purpose i/o (gpio) pins when not configured for host port usage. 62 ha0 gpiob8 input input/output host address (ha0) ?this input provides the address selection for hi registers. this pin is disconnected internally. port b gpio (8) ?this pin is a general purpose i/o (gpio) pin when not configured for host port usage. table 3-1 56857 signal and package informat ion for the 100-pin lqfp (continued) pin no. signal name type description
introduction 56857 technical data, rev. 6 freescale semiconductor 13 63 ha1 gpiob9 input input/output host address (ha1) ?this input provides the address selection for hi registers. this pin is disconnected internally. port b gpio (9) ?this pin is a general purpose i/o (gpio) pin when not configured for host port usage. 64 ha2 gpiob10 input input/output host address (ha2) ?this input provides the address selection for hi registers. this pin is disconnected internally. port b gpio (10) ?this pin is a general purpose i/o (gpio) pin when not configured for host port usage. 65 hrwb hrd gpiob11 input input input/output host read/write (hrwb) ?when the hi08 is programmed to interface to a single-data-strobe host bus and the hi function is selected, this signal is the read/write input. these pins are disconnected internally. host read data (hrd ) ?this signal is the read data input when the hi08 is programmed to interface to a double-data-strobe host bus and the hi function is selected. port b gpio (11) ?this pin is a general purpose i/o (gpio) pin when not configured for host port usage. 83 hds hwr gpiob12 input input input/output host data strobe (hds ) ?when the hi08 is programmed to interface to a single-data-strobe host bus and the hi function is selected, this input enables a data transfer on the hi when hcs is asserted. these pins are disconnected internally. host write enable (hwr ) ?this signal is the write data input when the hi08 is programmed to interface to a double-data-strobe host bus and the hi function is selected. port b gpio (12) ?this pin is a general purpose i/o (gpio) pin when not configured for host port usage. 84 hcs gpiob13 input input/output host chip select (hcs ) ?this input is the chip se lect input for the host interface. these pins are disconnected internally. port b gpio (13) ?this pin is a general purpose i/o (gpio) pin when not configured for host port usage. table 3-1 56857 signal and package informat ion for the 100-pin lqfp (continued) pin no. signal name type description
56857 technical data, rev. 6 14 freescale semiconductor 85 hreq htrq gpiob14 open drain output open drain output input/output host request (hreq ) ?when the hi08 is programmed for hrms=0 functionality (typically used on a si ngle-data- strobe bus), this open drain output is used by the hi to request service from the host processor. the hreq may be connected to an interrupt request pin of a host processor, a transfer request of a dma controller, or a control input of external circuitry. these pins are disconnected internally. transmit host request (htrq ) ?this signal is the transmit host request output when the hi08 is pr ogrammed for hrms=1 functionality and is typically used on a double-data-strobe bus. port b gpio (14) ?this pin is a general purpose i/o (gpio) pin when not configured for host port usage. 86 hack hrrq gpiob15 input open drain output input/output host acknowledge (hack ) ?when the hi08 is programmed for hrms=0 functionality (typically used on a single-data-strobe bus), this input has two functions: (1) provide a host acknowledge signal for dma transfers or (2) to control handshaking and provide a host interrupt acknowledge compatible with the mc68000 family processors. these pins are disconnected internally during reset. receive host re quest (hrrq) ?this signal is the receive host request output when the hi08 is pr ogrammed for hrms=1 functionality and is typically used on a double-data-strobe bus. port b gpio (15) ?this pin is a general purpose i/o (gpio) pin when not configured for host port usage. 81 tio0 gpiog0 input /output input/output timer input/output (tio0) ?this pin can be independently configured to be either a timer input source or an output flag. port g gpio (0) ?this pin is a general purpose i/o (gpio) pin that can individually be programmed as an input or output pin. 79 tio1 gpiog1 input /output input/output timer input/output (tio1) ?this pin can be independently configured to be either a timer input source or an output flag. port g gpio (1) ?this pin is a general purpose i/o (gpio) pin that can individually be programmed as an input or output pin. 78 tio2 gpiog2 input /output input/output timer input/output (tio2) ?this pin can be independently configured to be either a timer input source or an output flag. port g gpio (2) ?this pin is a general purpose i/o (gpio) pin that can individually be programmed as an input or output pin. table 3-1 56857 signal and package informat ion for the 100-pin lqfp (continued) pin no. signal name type description
introduction 56857 technical data, rev. 6 freescale semiconductor 15 77 tio3 gpiog3 input /output input/output timer input/output (tio3) ?this pin can be independently configured to be either a timer input source or an output flag. port g gpio (3) ?this pin is a general purpose i/o (gpio) pin that can individually be programmed as an input or output pin. 15 irqa input external interrupt request a and b ?the irqa and irqb inputs are asynchronous external interrupt reques ts that indicate that an external device is requesting service. a schm itt trigger input is used for noise immunity. they can be programmed to be level-sensitive or negative-edge- triggered. if level-sensitive triggering is selected, an external pull-up resistor is required for wired-or operation. 16 irqb 10 mode a gpioh0 input input/output mode select (mode a) ?during the bootstrap pr ocess mode a selects one of the eight bootstrap modes. port h gpio (0) ?this pin is a general purpose i/o (gpio) pin after the bootstrap process has completed. 11 mode b gpioh1 input input/output mode select (mode b) ?during the bootstrap pr ocess mode b selects one of the eight bootstrap modes. port h gpioh1 ?this pin is a general purpose i/o (gpio) pin after the bootstrap process has completed. 12 mode c gpioh2 input input/output mode select (mode c) ?during the bootstrap process mode c selects one of the eight bootstrap modes. port h gpio (2) ?this pin is a general purpose i/o (gpio) pin after the bootstrap process has completed. 28 reset input reset (reset ) ?this input is a direct hardware reset on the processor. when reset is asserted low, the controller is initialized and placed in the reset state. a schmit t trigger input is used for noise immunity. when the reset pin is deasserted, the initial chip operating mode is latched from the mode a, mode b, and mode c pins. to ensure complete ha rdware reset, reset and trst should be asserted together. the only exception occurs in a debugging environment when a hardware reset is required and it is necessary not to reset the jtag/enhanced once modu le. in this case, assert reset , but do not assert trst . 27 rsto output reset output (rsto ) ?this output is asserted on any reset condition (external reset, low volt age, software or cop). 51 rxd0 gpioe0 input input/output serial receive data 0 (rxd0) ?this input receives byte-oriented serial data and transfers it to the sci 0 receive shift register. port e gpio (0) ?this pin is a general purpose i/o (gpio) pin that can individually be programmed as input or output pin. table 3-1 56857 signal and package informat ion for the 100-pin lqfp (continued) pin no. signal name type description
56857 technical data, rev. 6 16 freescale semiconductor 52 txd0 gpioe1 output(z) input/output serial transmit data 0 (txd0) ?this signal transmits data from the sci 0 transmit data register. port e gpio (1) ?this pin is a general purpose i/o (gpio) pin that can individually be programmed as input or output pin. 74 rxd1 gpioe2 input input/output serial receive data 1 (rxd1) ?this input receives byte-oriented serial data and transfers it to the sci 1 receive shift register. port e gpio (2) ?this pin is a general purpose i/o (gpio) pin that can individually be programmed as input or output pin. 75 txd1 gpioe3 output(z) input/output serial transmit data 1 (txd1) ?this signal transmits data from the sci 1 transmit data register. port e gpio (3) ?this pin is a general purpose i/o (gpio) pin that can individually be programmed as input or output pin. 92 std0 gpioc0 output input /output essi transmit data (std0) ?this output pin transmits serial data from the essi transmitter shift register. port c gpio (0) ?this pin is a general purpose i/o (gpio) pin when the essi is not in use. 93 srd0 gpioc1 input input /output essi receive data (srd0) ?this input pin receives serial data and transfers the data to the essi receive shift register. port c gpio (1) ?this pin is a general purpose i/o (gpio) pin when the essi is not in use. 94 sck0 gpioc2 input /output input/output essi serial clock (sck0) ?this bidirectional pin provides the serial bit rate clock for the transmit section of the essi. the clock signal can be continuous or gated and can be used by both the transmitter and receiver in synchronous mode. port c gpio (2) ?this pin is a general purpose i/o (gpio) pin when the essi is not in use. 95 sc00 gpioc3 input /output input/output essi serial cont rol pin 0 (sc00) ?the function of this pin is determined by the selection of either synchronous or asynchronous mode. for asynchronous mode, this pin will be used for the receive clock i/o. for synchronous mode, this pin is used ei ther for transmitter1 output or for serial i/o flag 0. port c gpio (3) ?this pin is a general purpose i/o (gpio) pin when the essi is not in use. table 3-1 56857 signal and package informat ion for the 100-pin lqfp (continued) pin no. signal name type description
introduction 56857 technical data, rev. 6 freescale semiconductor 17 96 sc01 gpioc4 input /output input/output essi serial cont rol pin 1 (sc01) ?the function of this pin is determined by the selection of either synchronous or asynchronous mode. for asynchronous mode, this pin is the receiver frame sync i/o. for synchronous mode, this pin is used ei ther for transmitter2 output or for serial i/o flag 1. port c gpio (4) ?this pin is a general purpose i/o (gpio) pin when the essi is not in use. 97 sc02 gpioc5 input /output input/output essi serial control pin 2 (sc02) ?this pin is used for frame sync i/o. sc02 is the frame sync for both the transmitter and receiver in synchronous mode and for the transmitter only in asynchronous mode. when configured as an output, this pi n is the internally generated frame sync signal. when configured as an input, this pin receives an external frame sync signal for the transmitter (and the receiver in synchronous operation). port c gpio (5) ?this pin is a general purpose i/o (gpio) pin when the essi is not in use. 66 std1 gpiod0 output input /output essi transmit data (std1) ?this output pin transmits serial data from the essi transmitter shift register. port d gpiod0 ?this pin is a general purpose i/o (gpio) pin when the essi is not in use. 67 srd1 gpiod1 input input/ output essi receive data (srd1) ?this input pin receives serial data and transfers the data to the essi receive shift register. port d gpio (1) ?this pin is a general purpose i/o (gpio) pin when the essi is not in use. 68 sck1 gpiod2 input /output input/output essi serial clock (sck1) ?this bidirectional pin provides the serial bit rate clock for the transmit section of the essi. the clock signal can be continuous or gated and can be used by both the transmitter and receiver in synchronous mode. port d gpio (2) ?this pin is a general purpose i/o (gpio) pin when the essi is not in use. 69 sc10 gpiod3 input /output input/output essi serial cont rol pin 0 (sc10) ?the function of this pin is determined by the selection of either synchronous or asynchronous mode. for asynchronous mode, this pin will be used for the receive clock i/o. for synchronous mode, this pin is used ei ther for transmitter1 output or for serial i/o flag 0. port d gpio (3) ?this pin is a general purpose i/o (gpio) pin when the essi is not in use. table 3-1 56857 signal and package informat ion for the 100-pin lqfp (continued) pin no. signal name type description
56857 technical data, rev. 6 18 freescale semiconductor 70 sc11 gpiod4 input /output input/output essi serial cont rol pin 1 (sc11) ?the function of this pin is determined by the selection of either synchronous or asynchronous mode. for asynchronous mode, this pin is the receiver frame sync i/o. for synchronous mode, this pin is used ei ther for transmitter2 output or for serial i/o flag 1. port d gpio (4) ?this pin is a general purpose i/o (gpio) pin when the essi is not in use. 71 sc12 gpiod5 input /output input/output essi serial control pin 2 (sc12) ?this pin is used for frame sync i/o. sc02 is the frame sync for both the transmitter and receiver in synchronous mode and for the transmitter only in asynchronous mode. when configured as an output, this pi n is the internally generated frame sync signal. when configured as an input, this pin receives an external frame sync signal for the transmitter (and the receiver in synchronous operation). port d gpio (5) ?this pin is a general purpose i/o (gpio) pin when the essi is not in use. 1miso gpiof0 input /output input/output spi master in/slave out (miso) ?this serial data pin is an input to a master device and an output from a slave device. the miso line of a slave device is placed in the high-impedance state if the slave device is not selected. the driver on this pi n can be configured as an open-drain driver by the spi?s wired-or mode (w om) bit when this pin is configured for spi operation. port f gpio (0) ?this pin is a general purpose i/o (gpio) pin that can individually be programmed as input or output pin. 2mosi gpiof1 input / output (z) input/output spi master out/slave in (mosi) ?this serial data pin is an output from a master device and an input to a slave device. the master device places data on the mosi line a half-cycle before the clock edg e that the slave device uses to latch the data. the driv er on this pin can be configured as an open-drain driver by t he spi?s wom bit when this pin is configured for spi operation. port f gpio (1) ?this pin is a general purpose i/o (gpio) pin that can be individually programmed as input or output pin. table 3-1 56857 signal and package informat ion for the 100-pin lqfp (continued) pin no. signal name type description
introduction 56857 technical data, rev. 6 freescale semiconductor 19 3sck gpiof2 input/ output input/output spi serial clock (sck) ?this bidirectional pin provides a serial bit rate clock for the spi. this gated clock signa l is an input to a slave device and is generated as an output by a mast er device. slave devices ignore the sck signal unless the ss pin is active low. in both master and slave spi devices, data is shifted on one edge of the sck signal and is sampled on the opposite edge where data is stabl e. the driver on this pin can be configured as an open-drain driver by the spi?s wom bit when this pin is configured for spi operation. when us ing wired-or mode, the user must provide an external pull-up device. port f gpio (2) ?this pin is a general purpose i/o (gpio) pin that can individually be programmed as input or output pin. 4ss gpiof3 input input/output spi slave select (ss ) ?this input pin selects a slave device before a master device can exchange data with the slave device. ss must be low before data transactions and must stay low for the duration of the transaction. the ss line of the master must be held high. port f gpio (3) ?this pin is a general purpose i/o (gpio) pin that can individually be programmed as input or output pin. 20 xtal input/ output crystal oscillator output (xtal) ?this output connects the internal crystal oscillator output to an external crystal. if an external clock source other than a crystal oscillator is used , xtal must be used as the input. 21 extal input external crystal osc illator input (extal) ?this input should be connected to an external crystal. if an external clock source other than a crystal oscillator is used, extal must be tied off. see section 4.5.2 26 clko output clock output (clko) ?this pin outputs a buffered clock signal. when enabled, this signal is the system clock divided by four. 44 tck input test clock input (tck) ?this input pin provides a gated clock to synchronize the test logic and to shift serial data to the jtag/enhanced once port. the pin is connected internally to a pull-down resistor. 42 tdi input test data input (tdi) ?this input pin provides a serial input data stream to the jtag/enhanced once port. it is sampled on the rising edge of tck and has an on-chip pull-up resistor. 41 tdo output(z) test data output (tdo) ?this tri-statable output pin provides a serial output data stream from the jtag/enhanced once port. it is driven in the shift-ir and shift-dr controller states, and changes on the falling edge of tck. 43 tms input test mode select input (tms) ?this input pin is used to sequence the jtag tap controller?s stat e machine. it is sampled on the rising edge of tck and has an on-chip pull-up resistor. note: always tie the tms pin to v dd through a 2.2k resistor. table 3-1 56857 signal and package informat ion for the 100-pin lqfp (continued) pin no. signal name type description
56857 technical data, rev. 6 20 freescale semiconductor 40 trst input test reset (trst ) ?as an input, a low signal on this pin provides a reset signal to the jtag tap controller. to ensure complete hardware reset, trst should be asserted whenever reset is asserted. the only exception occurs in a debugging environment, since the enhanced once/jtag module is under the control of the debugger. in this case it is not necessary to assert trst when asserting reset . outside of a debugging environment reset should be permanently asserted by grounding the signal, thus disabli ng the enhanced once/jtag module on the device. note: for normal operation, connect trst directly to v ss . if the design is to be used in a debugging environment, trst may be tied to v ss through a 1k resistor. 39 de input /output debug event (de ) ?this is an open-drain, bidirectional, active low signal. as an input, it is a means of entering debug mode of operation from an external command controller. as an output, it is a means of acknowledging that the chip has entered debug mode. this pin is connected internally to a weak pull-up resistor. table 3-1 56857 signal and package informat ion for the 100-pin lqfp (continued) pin no. signal name type description
general characteristics 56857 technical data, rev. 6 freescale semiconductor 21 part 4 specifications 4.1 general characteristics the 56857 is fabricated in high-dens ity cmos with 5-volt tolerant tt l-compatible digital inputs. the term ?5-volt tolerant? refers to the capability of an i/o pin, bui lt on a 3.3v comp atible process technology, to withstand a voltage up to 5.5v wit hout damaging the device. many systems have a mixture of devices designe d for 3.3v and 5v power supplies. in such systems, a bus may carry both 3.3v and 5v- compatible i/o voltage levels (a standard 3.3v i/o is designed to receive a maximum voltage of 3.3v 10% during normal operat ion without causing damage). this 5v tolerant capability therefore offers the power savings of 3.3v i/o levels while being able to receive 5v levels without being damaged. absolute maximum ratings given in table 4-1 are stress ratings only, and functional operation at the maximum is not guaranteed. stress beyond these ratings may affect device reliability or cause permanent damage to the device. the 56857 dc/ac electrical specificat ions are preliminar y and are from desi gn simulations. these specifications may not be fully tested or guaranteed at this early stage of the product life cycle. finalized specifications will be published af ter complete characterization a nd device qualificat ions have been completed. caution this device contains protective circuitry to guard against damage due to high static voltage or electrical fields. however, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level.
56857 technical data, rev. 6 22 freescale semiconductor table 4-1 absolute maximum ratings characteristic symbol min max unit supply voltage, core v dd 1 1. v dd must not exceed v ddio v ss ? 0.3 v ss + 2.0 v supply voltage, io supply voltage, analog v ddio 2 v ddio 2 2. v ddio and v dda must not differ by more that 0.5v v ssio ? 0.3 v ssa ? 0.3 v ssio + 4.0 v dda + 4.0 v digital input voltages analog input voltages (xtal, extal) v in v ina v ssio ? 0.3 v ssa ? 0.3 v ssio + 5.5 v dda + 0.3 v current drain per pin excluding v dd , gnd i ? 8 ma junction temperature t j -40 120 c storage temperature range t stg -55 150 c table 4-2 recommended operating conditions characteristic symbol min max unit supply voltage for logic power v dd 1.62 1.98 v supply voltage for i/o power v ddio 3.0 3.6 v supply voltage for analog power v dda 3.0 3.6 v ambient operating temperature t a -40 85 c pll clock frequency 1 1. assumes clock source is direct clo ck to extal or crystal os cillator running 2-4mhz. pll must be enabled, locked, and selected. the actual frequency depends on the source clock frequency and programming of the cgm module. f pll ?240mhz operating frequency 2 2. master clock is derived from on of the following four sources: f clk = f xtal when the source clock is the direct clock to extal f clk = f pll when pll is selected f clk = f osc when the source clock is the crystal oscillator and pll is not selected f clk = f extal when the source clock is the direct cl ock to extal and pll is not selected f op ?120mhz frequency of peripheral bus f ipb ?60mhz frequency of external clock f clk ?240mhz frequency of oscillator f osc 24mhz frequency of cl ock via xtal f xtal ?240mhz frequency of cl ock via extal f extal 24mhz
dc electrical characteristics 56857 technical data, rev. 6 freescale semiconductor 23 4.2 dc electrical characteristics table 4-3 thermal characteristics 1 1. see section 6.1 for more detail. characteristic 100-pin lqfp symbol value unit thermal resistance junction-to-ambient (estimated) ja 41.2 c/w i/o pin power dissipation p i/o user determined w power dissipation p d p d = (i dd v dd ) + p i/o w maximum allowed p d p dmax (t j ? t a ) / r ja 2 2. tj = junction temperature ta = ambient temperature w table 4-4 dc electr ical characteristics operating conditions: v ss = v ssio = v ssa = 0 v, v dd = 1.62-1.98v, v ddio = v dda = 3.0?3.6v, t a = ?40 to +120 c, c l 50pf, f op = 120mhz characteristic symbol min typ max unit input high voltage (xtal/extal) v ihc v dda ? 0.8 v dda v dda + 0.3 v input low voltage (xtal/extal) v ilc -0.3 ? 0.5 v input high voltage v ih 2.0 ? 5.5 v input low voltage v il -0.3 ? 0.8 v input current low (pullups disabled) i il -1 ? 1 a input current high (pullups disabled) i ih -1 ? 1 a output tri-state current low i ozl -10 ? 10 a output tri-state current high i ozh -10 ? 10 a output high voltage v oh v ddio ? 0.7 ? ? v output low voltage v ol ??0.4v output high current i oh 8?16ma output low current i ol 8?16ma input capacitance c in ?8?pf output capacitance c out ?12?pf v dd supply current (core logic, memories, peripherals) run 1 deep stop 2 light stop 3 i dd 4 ? ? ? 70 0.05 5 110 10 14 ma ma ma
56857 technical data, rev. 6 24 freescale semiconductor figure 4-1 maximum run i ddtotal vs. frequency (see notes 1. and 5. in table 4-4 ) v ddio supply current (i/o circuity) run 5 deep stop 2 i ddio ?40 0 50 1.5 ma ma v dda supply current (analog circuity) deep stop 2 i dda ?60120 a low voltage interrupt 6 v ei ? 2.5 2.85 v low voltage interrupt recovery hysteresis v eih ?50?mv power on reset 7 por ? 1.5 2.0 v note: run (operating) i dd measured using external sq uare wave clock source (f osc = 4mhz) into xtal. all inputs 0.2v from rail; no dc loads; outputs unloaded. all ports conf igured as inputs; measured with all modules enabled. pll set to 240mhz out. 1. running core, performing 50% nop and 50% fir. clock at 120 mhz. 2. deep stop mode - operation frequency = 4 mhz, pll set to 4 mhz, crystal oscillator and time of day module operating. 3. light stop mode - operation frequency = 120 mhz, pll set to 2 40 mhz, crystal oscillator and time of day module operating. 4. i dd includes current for core logic, internal memo ries, and all internal per ipheral logic circuitry. 5. running core and performing external memory access. clock at 120 mhz. 6. when v dd drops below v ei max value, an interrupt is generated. 7. power-on reset occurs whenever the digital supply drops below 1.8v. while power is ramping up, this signal remains active for as long as the internal 2.5v is below 1.8v no matter how long the ramp up rate is. the internally regulated voltage is typi cally 100 mv less than v dd during ramp up until 2.5v is reached, at which time it self-regulates. table 4-4 dc electrical characteristics (continued) operating conditions: v ss = v ssio = v ssa = 0 v, v dd = 1.62-1.98v, v ddio = v dda = 3.0?3.6v, t a = ?40 to +120 c, c l 50pf, f op = 120mhz characteristic symbol min typ max unit 0 30 60 120 150 20 40 60 80 100 120 idd (ma) 90 emi mode 5 mac mode 1
supply voltage sequencing and separation cautions 56857 technical data, rev. 6 freescale semiconductor 25 4.3 supply voltage sequencing and separation cautions figure 4-2 shows two situations to avoid in sequencing the v dd and v ddio, v dda supplies. note: 1. v dd rising before v ddio , v dda 2. v ddio , v dda rising much faster than v dd figure 4-2 supply voltage seque ncing and separation cautions v dd should not be allowed to rise ea rly (1). this is usua lly avoided by running the regulator for the v dd supply (1.8v) from the voltage generated by the 3.3v v ddio supply, see figure 4-3 . this keeps v dd from rising faster than v ddio . v dd should not rise so late that a large voltage difference is al lowed between the two supplies (2). typically this situation is avoided by using external di screte diodes in series between supplies, as shown in figure 4-3 . the series diodes forward bias when the difference between v ddio and v dd reaches approximately 2.1, causing v dd to rise as v ddio ramps up. when the v dd regulator begins proper operation, the difference between suppl ies will typically be 0.8v and conduction thr ough the diode chain reduces to essentially leakage current. during supply se quencing, the following general relationship should be adhered to: v ddio > v dd > (v ddio - 2.1v) in practice, v dda is typically connected directly to v ddio with some filtering. figure 4-3 example circuit to control supply sequencing 3.3v 1.8v time 0 2 1 supplies stable v dd v ddio, v dda dc power supply voltage 3.3v regulator 1.8v regulator supply v dd v ddio, v dda
56857 technical data, rev. 6 26 freescale semiconductor 4.4 ac electrical characteristics timing waveforms in section 4.4 are tested with a v il maximum of 0.8v and a v ih minimum of 2.0v for all pins except xtal, which is te sted using the input levels in section 4.2 . in figure 4-4 the levels of v ih and v il for an input signal are shown. figure 4-4 input signal measurement references figure 4-5 shows the definitions of the following signal states: ? active state, when a bus or signal is driven, and enters a low impedance state ? tri-stated, when a bus or signal is placed in a high impedance state ? data valid state, when a signal level has reached v ol or v oh ? data invalid state, when a signal level is in transition between v ol and v oh figure 4-5 signal states v ih v il fall time input signal note: the midpoint is v il + (v ih ? v il )/2. midpoint1 low high 90% 50% 10% rise time data invalid state data1 data2 valid data tri-stated data3 valid data2 data3 data1 valid data active data active
external clock operation 56857 technical data, rev. 6 freescale semiconductor 27 4.5 external clock operation the 56857 system clock can be derived from a crys tal or an external system clock signal. to generate a reference frequency using the intern al oscillator, a reference crysta l must be connected between the extal and xtal pins. 4.5.1 crystal oscillator the internal oscillator is designed to interface with a parallel-resonant crystal resonator in the frequency range specified for the external crystal in table 4-6 . in figure 4-6 a typical crystal os cillator circuit is shown. follow the crystal supplier? s recommendations when selecti ng a crystal, because crystal parameters determine the component values required to provide maximu m stability and reliable start-up. the crystal and associated compone nts should be mounted as close as possible to the extal and xtal pins to minimize output distortion and start-up stabilization time. figure 4-6 crystal oscillator 4.5.2 high speed external clock source (> 4mhz) the recommended method of connecting an external clock is given in figure 4-7 . the external clock source is connected to xtal and the extal pin is held at ground, v dda , or v dda /2. the tod_sel bit in cgm must be set to 0. figure 4-7 connecting a high speed external clock signal using xtal 4.5.3 low speed external clock source (2-4mhz) the recommended method of connecting an external clock is given in figure 4-8 . the external clock source is connected to xtal a nd the extal pin is held at v dda /2. the tod_sel bit in cgm must be set to 0. sample external crystal parameters: r z = 10m tod_sel bit in cgm must be set to 0 crystal frequency = 2?4mhz (optimized for 4mhz) extal xtal r z 56857 xtal extal external gnd, v dda , clock (up to 240mhz) or v dda /2
56857 technical data, rev. 6 28 freescale semiconductor figure 4-8 connecting a low speed external clock signal using xtal figure 4-9 external clock timing table 4-5 external clock op eration timing requirements 4 operating conditions: v ss = v ssio = v ssa = 0 v, v dd = 1.62-1.98v, v ddio = v dda = 3.0?3.6v, t a = ?40 to +120 c, c l 50pf, f op = 120mhz characteristic symbol min typ max unit frequency of operation (external clock driver) 1 1. see figure 4-7 for details on using the recommended connec tion of an external clock driver. f osc 0 ? 240 mhz clock pulse width 4 t pw 6.25 ? ? ns external clock input rise time 2, 4 2. external clock input rise time is measured from 10% to 90%. t rise ??tbdns external clock input fall time 3, 4 3. external clock input fall time is measured from 90% to 10%. 4. parameters listed are guaranteed by design. t fall ??tbdns 56857 xtal extal external clock (2-4mhz) v dda /2 external clock v ih v il note: the midpoint is v il + (v ih ? v il )/2. 90% 50% 10% 90% 50% 10% t pw t pw t fall t rise
reset, stop, wait, mode select, and interrupt timing 56857 technical data, rev. 6 freescale semiconductor 29 4.6 reset, stop, wait, mode select, and interrupt timing table 4-6 pll timing operating conditions: v ss = v ssio = v ssa = 0 v, v dd = 1.62-1.98v, v ddio = v dda = 3.0?3.6v, t a = ?40 to +120 c, c l 50pf, f op = 120mhz characteristic symbol min typ max unit external reference crystal frequency for the pll 1 1. an externally supplied refer ence clock should be as free as possible from any phase jitter for the pll to work correctly. the pll is optimized for 4mhz input crystal. f osc 244mhz pll output frequency f clk 40 ? 240 mhz pll stabilization time 2 2. this is the minimum time required after the pll setup is changed to ensure reliable operation. t plls ?110ms table 4-7 reset, stop, wait, mode select, and interrupt timing 1, 2 operating conditions: v ss = v ssio = v ssa = 0 v, v dd = 1.62-1.98v, v ddio = v dda = 3.0?3.6v, t a = ?40 to +120 c, c l 50pf, f op = 120mhz 1. in the formulas, t = clock cycle. for f op = 120mhz operation and f ipb = 60mhz, t = 8.33ns. 2. parameters listed are guaranteed by design. characteristic symbol typ min typ max unit see figure minimum reset assertion duration 3 3. at reset, the pll is disabled and bypassed. the part is then put into run mode and t clk assumes the period of the source clock, t xtal , t extal or t osc . t ra 30 ? ns 4-10 edge-sensitive interrupt request width t irw 1t + 3 ? ns 4-11 irqa , irqb assertion to general purpose output valid, caused by first instruction execution in the interrupt service routine t ig 18t ? ns 4-12 irqa width assertion to recover from stop state t iw 2t ? ns 4-13 delay from irqa assertion to fetch of first instruction (exiting stop) 4 fast 5 normal 6, 7 4. this interrupt instruction fetch is visible on the pins only in mode 3. 5. fast stop mode: fast stop recovery applies when external clocking is in use (direct clocking to xtal) or when fast stop mode recovery is reque st- ed (omr bit 6 is set to 1). in both cases the pll and the master clock are unaffected by stop mode entry. recovery takes one le ss cycle and t clk will continue with the same value it had before stop mode was entered. 6. normal stop mode: as a power saving feature, normal stop mode disables and bypasse s the pll. stop mode will then shut down the master clock, recovery will take an extra c ycle (to restart the clock), and t clk will resume at the input clock source rate. t if ? ? 13t 25et ns ns 4-13 rsto pulse width 7 normal operation internal reset mode 7. et = external clock period; for an ex ternal crystal frequency of 4mhz, et=250ns. t rsto 128et 8et ? ? ? ? 4-14
56857 technical data, rev. 6 30 freescale semiconductor figure 4-10 asynchronous reset timing figure 4-11 external interrupt ti ming (negative-edge-sensitive) figure 4-12 external level-s ensitive interrupt timing figure 4-13 recovery from stop state using asynchronous interrupt timing figure 4-14 reset output timing reset t ra irqa irqb t irw purpose i/o pin irqa , irqb b) general purpose i/o t ig general irqa t iw reset t rsto
host interface port 56857 technical data, rev. 6 freescale semiconductor 31 4.7 host interface port table 4-8 host interface port timing 1 operating conditions: v ss = v ssio = v ssa = 0 v, v dd = 1.62-1.98v, v ddio = v dda = 3.0?3.6v, t a = ?40 to +120 c, c l 50pf, f op = 120mhz 1. the formulas: t = clock cycle. f ipb = 60mhz, t = 16.7ns. characteristic symbol min max unit see figure access time tackdv ?13ns 4-19 disable time tackdz 3?ns 4-19 time to disassert tackreqh 3.5 9 ns 4-19 4-22 lead time treqackl 0?ns 4-19 4-22 access time tradv ?13 ns 4-20 4-21 disable time tradx 5? ns 4-20 4-21 disable time tradz 3? ns 4-20 4-21 setup time tdacks 3?ns 4-22 hold time tackdh 1?ns 4-22 setup time tadss 3?ns 4-23 4-24 hold time tdsah 1?ns 4-23 4-24 pulse width twds 5?ns 4-23 4-24 time to re-assert 1. after second write in 16-bit mode 2. after first write in 16-bit mode or after write in 8-bit mode tackreql 4t + 5 5 5t + 9 13 ns ns 4-19 4-22
56857 technical data, rev. 6 32 freescale semiconductor figure 4-15 controller-to -host dma read model figure 4-16 single strobe read mode figure 4-17 dual strobe read mode hack hd hreq tackdv tackdz treqackl tackreql tackreqh tradv tradz tradx ha hcs hds hd hrw tradv tradz tradx ha hcs hwr hd hrd
host interface port 56857 technical data, rev. 6 freescale semiconductor 33 figure 4-18 host-to-cont roller dma write mode figure 4-19 single st robe write mode figure 4-20 dual st robe write mode hack hreq hd tdacks tackdh treqackl tackreql tackreqh ha hcs hds hd hrw tadss tadss tdsah tdsah twds tdsah ha hcs hwr hd hrd twds tadss tadss tdsah
56857 technical data, rev. 6 34 freescale semiconductor 4.8 serial peripheral interface (spi) timing 1. parameters listed are guaranteed by design. table 4-9 spi timing 1 operating conditions: v ss = v ssio = v ssa = 0 v, v dd = 1.62-1.98v, v ddio = v dda = 3.0?3.6v, t a = ?40 to +120 c, c l 50pf, f op = 120mhz characteristic symbol min max unit see figure cycle time master slave t c 25 25 ? ? ns ns 4-21 , 4-22 , 4-23 , 4-24 enable lead time master slave t eld ? 12.5 ? ? ns ns 4-24 enable lag time master slave t elg ? 12.5 ? ? ns ns 4-24 clock (sclk) high time master slave t ch 9 12.5 ? ? ns ns 4-21 , 4-22 , 4-23 , 4-24 clock (sclk) low time master slave t cl 12 12.5 ? ? ns ns 4-24 data set-up time required for inputs master slave t ds 10 2 ? ? ns ns 4-21 , 4-22 , 4-23 , 4-24 data hold time required for inputs master slave t dh 0 2 ? ? ns ns 4-21 , 4-22 , 4-23 , 4-24 access time (time to data active from high-impedance state) slave t a 515 ns ns 4-24 disable time (hold time to high-impedance state) slave t d 29 ns ns 4-24 data valid for outputs master slave (after enable edge) t dv ? ? 2 14 ns ns 4-21 , 4-22 , 4-23 , 4-24 data invalid master slave t di 0 0 ? ? ns ns 4-21 , 4-22 , 4-23 , 4-24 rise time master slave t r ? ? 11.5 10.0 ns ns 4-21 , 4-22 , 4-23 , 4-24 fall time master slave t f ? ? 9.7 9.0 ns ns 4-21 , 4-22 , 4-23 , 4-24
serial peripheral interface (spi) timing 56857 technical data, rev. 6 freescale semiconductor 35 figure 4-21 spi master timing (cpha = 0) figure 4-22 spi master timing (cpha = 1) sclk (cpol = 0) (output) sclk (cpol = 1) (output) miso (input) mosi (output) msb in bits 14?1 lsb in master msb out bits 14?1 master lsb out ss (input) ss is held high on master t c t r t f t ch t cl t f t r t ch t ch t dv t dh t ds t di t di (ref) t f t r t cl sclk (cpol = 0) (output) sclk (cpol = 1) (output) miso (input) mosi (output) msb in bits 14?1 lsb in master msb out bits 14? 1 master lsb out ss (input) ss is held high on master t r t f t c t ch t cl t ch t cl t f t ds t dh t r t di t dv (ref) t dv t f t r
56857 technical data, rev. 6 36 freescale semiconductor figure 4-23 spi slave timing (cpha = 0) figure 4-24 spi slave timing (cpha = 1) sclk (cpol = 0) (input) sclk (cpol = 1) (input) miso (output) mosi (input) slave msb out bits 14?1 msb in bits 14?1 lsb in ss (input) slave lsb out t ds t cl t cl t di t di t ch t ch t r t r t elg t dh t eld t c t f t f t d t a t dv sclk (cpol = 0) (input) sclk (cpol = 1) (input) miso (output) mosi (input) slave msb out bits 14?1 msb in bits 14?1 lsb in ss (input) slave lsb out t elg t di t ds t dh t eld t c t cl t ch t r t f t f t cl t ch t dv t a t dv t r t d
quad timer timing 56857 technical data, rev. 6 freescale semiconductor 37 4.9 quad timer timing figure 4-25 timer timing 4.10 enhanced synchronous se rial interface (essi) timing table 4-10 quad timer timing 1, 2 operating conditions: v ss = v ssio = v ssa = 0 v, v dd = 1.62-1.98v, v ddio = v dda = 3.0?3.6v, t a = ?40 to +120 c, c l 50pf, f op = 120mhz 1. in the formulas listed, t = clock cycle. for f op = 120mhz operation and fipb = 60mhz, t = 8.33ns. 2. parameters listed are guaranteed by design. characteristic symbol min max unit timer input period p in 2t + 3 ? ns timer input high/low period p inhl 1t + 3 ? ns timer output period p out 2t - 3 ? ns timer output high/low period p outhl 1t - 3 ? ns table 4-11 essi master mode 1 switching characteristics operating conditions: v ss = v ssio = v ssa = 0 v, v dd = 1.62-1.98v, v ddio = v dda = 3.0?3.6v, t a = ?40 to +120 c, c l 50pf, f op = 120mhz parameter symbol min typ max units sck frequency fs ? ? 15 2 mhz sck period 3 t sckw 66.7 ? ? ns sck high time t sckh 33.4 4 ?? ns sck low time t sckl 33.4 4 ?? ns output clock rise/fall time ? ? 4 ? ns timer inputs timer outputs p inhl p inhl p in p outhl p outhl p out
56857 technical data, rev. 6 38 freescale semiconductor delay from sck high to sc2 (bl) high - master 5 t tfsbhm -1.0 ? 1.0 ns delay from sck high to sc2 (wl) high - master 5 t tfswhm -1.0 ? 1.0 ns delay from sc0 high to sc1 (bl) high - master 5 t rfsbhm -1.0 ? 1.0 ns delay from sc0 high to sc1 (wl) high - master 5 t rfswhm -1.0 ? 1.0 ns delay from sck high to sc2 (bl) low - master 5 t tfsblm -1.0 ? 1.0 ns delay from sck high to sc2 (wl) low - master 5 t tfswlm -1.0 ? 1.0 ns delay from sc0 high to sc1 (bl) low - master 5 t rfsblm -1.0 ? 1.0 ns delay from sc0 high to sc1 (wl) low - master 5 t rfswlm -1.0 ? 1.0 ns sck high to std enable from high impedance - master t txem -0.1 ? 2 ns sck high to std valid - master t txvm -0.1 ? 2 ns sck high to std not valid - master t txnvm -0.1 ? ? ns sck high to std high impedance - master t txhim -4 ? 0 ns srd setup time before sc0 low - master t sm 4??ns srd hold time after sc0 low - master t hm 4??ns synchronous operation (in addition to standard internal clock parameters) srd setup time before sck low - master t tsm 4??ns srd hold time after sck low - master t thm 4??ns 1. master mode is internally generated clocks and frame syncs 2. max clock frequency is ip_clk/4 = 60mhz / 4 = 15mhz for an 120mhz part. 3. all the timings for the essi are given for a non-inverted se rial clock polarity (tsckp=0 in scr2 and rsckp=0 in scsr) and a non-inverted frame sync (tfsi=0 in scr2 and rfsi=0 in scsr). if the polarity of the clock and/or the frame sync have been inverted, all the timings remain valid by inverting the clock signal sck/sc0 and/or the frame sync sc2/sc1 in the tables and in the figures. 4. 50 percent duty cycle 5. bl = bit length; wl = word length table 4-11 essi master mode 1 switching charact eristics (continued) operating conditions: v ss = v ssio = v ssa = 0 v, v dd = 1.62-1.98v, v ddio = v dda = 3.0?3.6v, t a = ?40 to +120 c, c l 50pf, f op = 120mhz parameter symbol min typ max units
enhanced synchronous serial interface (essi) timing 56857 technical data, rev. 6 freescale semiconductor 39 figure 4-26 master mo de timing diagram table 4-12 essi slave mode 1 switching characteristics operating conditions: v ss = v ssio = v ssa = 0 v, v dd = 1.62-1.98v, v ddio = v dda = 3.0?3.6v, t a = ?40 to +120 c, c l 50pf, f op = 120mhz parameter symbol min typ max units sck frequency fs ? ? 15 2 mhz sck period 3 t sckw 66.7 ? ? ns sck high time t sckh 33.4 4 ?? ns sck low time t sckl 33.4 4 ?? ns output clock rise/fall time ? ? 4 ? ns delay from sck high to sc2 (bl) high - slave 5 t tfsbhs -1 ? 29 ns delay from sck high to sc2 (wl) high - slave 5 t tfswhs -1 ? 29 ns t thm t tsm t hm t sm t rfswlm t rfswhm t rfblm t rfsbhm t txhim t txnvm t txvm t txem t tfswlm t tfswhm t tfsblm t tfsbhm t sckl t sckw t sckh first bit last bit sck output sc2 (bl) output sc2 (wl) output std sc0 output sc1 (bl) output sc1 (wl) output srd
56857 technical data, rev. 6 40 freescale semiconductor delay from sc0 high to sc1 (bl) high - slave 5 t rfsbhs -1 ? 29 ns delay from sc0 high to sc1 (wl) high - slave 5 t rfswhs -1 ? 29 ns delay from sck high to sc2 (bl) low - slave 5 t tfsbls -29 ? 29 ns delay from sck high to sc2 (wl) low - slave 5 t tfswls -29 ? 29 ns delay from sc0 high to sc1 (bl) low - slave 5 t rfsbls -29 ? 29 ns delay from sc0 high to sc1 (wl) low - slave 5 t rfswls -29 ? 29 ns sck high to std enable from high impedance - slave t txes ??15 ns sck high to std valid - slave t txvs 4?15ns sc2 high to std enable from high impedance (first bit) - slave t ftxes 4?15ns sc2 high to std valid (first bit) - slave t ftxvs 4?15ns sck high to std not valid - slave t txnvs 4?15ns sck high to std high impedance - slave t txhis 4?15ns srd setup time befor e sc0 low - slave t ss 4??ns srd hold time after sc0 low - slave t hs 4??ns synchronous operation (in addition to standard external clock parameters) srd setup time befor e sck low - slave t tss 4??ns srd hold time afte r sck low - slave t ths 4??ns 1. slave mode is externally generated clocks and frame syncs 2. max clock frequency is ip_clk/4 = 60mhz / 4 = 15mhz for a 120mhz part. 3. all the timings for the essi are given for a non-inverted se rial clock polarity (tsckp=0 in scr2 and rsckp=0 in scsr) and a non-inverted frame sync (tfsi=0 in scr2 and rfsi=0 in scsr). if the polarity of the clock and/or the frame sync have been inverted, all the timings remain valid by inverting the clock signal sck/sc0 and/or the frame sync sc2/sc1 in the tables and in the figures. 4. 50 percent duty cycle 5. bl = bit length; wl = word length table 4-12 essi slave mode 1 switching charact eristics (continued) operating conditions: v ss = v ssio = v ssa = 0 v, v dd = 1.62-1.98v, v ddio = v dda = 3.0?3.6v, t a = ?40 to +120 c, c l 50pf, f op = 120mhz parameter symbol min typ max units
serial communication interface (sci) timing 56857 technical data, rev. 6 freescale semiconductor 41 figure 4-27 slave m ode clock timing 4.11 serial communication interface (sci) timing table 4-13 sci timing 4 operating conditions: v ss = v ssio = v ssa = 0 v, v dd = 1.62-1.98v, v ddio = v dda = 3.0?3.6v, t a = ?40 to +120 c, c l 50pf, f op = 120mhz characteristic symbol min max unit baud rate 1 1. f max is the frequency of operation of the system clock in mhz. br ? (f max )/(32) mbps rxd 2 pulse width 2. the rxd pin in sci0 is named rxd0 and the rxd pin in sci1 is named rxd1. rxd pw 0.965/br 1.04/br ns txd 3 pulse width 3. the txd pin in sci0 is named txd0 and the txd pin in sci1 is named txd1. 4. parameters listed are guaranteed by design. txd pw 0.965/br 1.04/br ns t ths t tss t hs t ss t rfswls t rfswhs t rfbls t rfsbhs t txhis t txnvs t ftxvs t txvs t ftxes t txes t tfswls t tfswhs t tfsbls t tfsbhs t sckl t sckw t sckh first bit last bit sck input sc2 (bl) input sc2 (wl) input std sc0 input sc1 (bl) input sc1 (wl) input srd
56857 technical data, rev. 6 42 freescale semiconductor figure 4-28 rxd pulse width figure 4-29 txd pulse width 4.12 jtag timing table 4-14 jtag timing 1, 3 operating conditions: v ss = v ssio = v ssa = 0 v, v dd = 1.62-1.98v, v ddio = v dda = 3.0?3.6v, t a = ?40 to +120 c, c l 50pf, f op = 120mhz 1. timing is both wait state and frequency dependent. fo r the values listed, t = clock cycle. for 120mhz operation, t = 8.33ns. characteristic symbol min max unit tck frequency of operation 2 2. tck frequency of operation must be less than 1/4 the processor rate. 3. parameters listed are guaranteed by design. f op dc 30 mhz tck cycle time t cy 33.3 ? ns tck clock pulse width t pw 16.6 ? ns tms, tdi data setup time t ds 3?ns tms, tdi data hold time t dh 3?ns tck low to tdo data valid t dv ?12ns tck low to tdo tri-state t ts ?10ns trst assertion time t trst 35 ? ns de assertion time t de 4t ? ns rxd sci receive data pin (input) rxd pw txd sci receive data pin (input) txd pw
jtag timing 56857 technical data, rev. 6 freescale semiconductor 43 figure 4-30 test clock input timing diagram figure 4-31 test access po rt timing diagram figure 4-32 t rst timing diagram figure 4-33 enhanced once?debug event tck (input) v m v il v m = v il + (v ih ? v il )/2 v m v ih t pw t pw t cy input data valid output data valid output data valid tck (input) tdi (input) tdo (output) tdo (output ) tdo (output) tms t dv t ts t dv t ds t dh trst (input) t trst de t de
56857 technical data, rev. 6 44 freescale semiconductor 4.13 gpio timing figure 4-34 gpio timing table 4-15 gpio timing 1, 2 operating conditions: v ss = v ssio = v ssa = 0 v, v dd = 1.62-1.98v, v ddio = v dda = 3.0?3.6v, t a = ?40 to +120 c, c l 50pf, f op = 120mhz 1. in the formulas listed, t = clock cycle. for f op = 120mhz operation and fipb = 60mhz, t = 8.33ns 2. parameters listed are guaranteed by design. characteristic symbol min max unit gpio input period p in 2t + 3 ? ns gpio input high/low period p inhl 1t + 3 ? ns gpio output period p out 2t - 3 ? ns gpio output high/low period p outhl 1t - 3 ? ns gpio inputs gpio outputs p inhl p inhl p in p outhl p outhl p out
package and pin-out information 56857 56857 technical data, rev. 6 freescale semiconductor 45 part 5 packaging 5.1 package and pin-out information 56857 this section contains package and pin-out information for the 100-pin lqfp configuration of the 56857. figure 5-1 top view, 56857 100-pin lqfp package pin 1 pin 26 pin 51 pin 76 miso mosi sck ss v ddio v ddio v ssio v dd v ss moda modb modc v ddio v ssio irqa irqb v dda v ssa v ssa xtal extal hd0 hd1 hd2 v dd clko rsto reset hd3 hd4 hd5 hd6 hd7 v ddio v ssio v dd v ss v ss de trst tdo tdi tms tck v ddio v ddio txd1 rxd1 v ssio v ddio sc12 sc11 sc10 sck1 srd1 std1 hrwb ha2 ha1 ha0 v ss v dd v dd cs3 cs2 cs1 cs0 v ssio v ddio txdo rxd0 v ssio esd v ddio sc02 sc01 sc00 sck0 srd0 std0 v ssio v ddio esd v ss v dd hack hreq hcs hds v ssio tio0 v ddio tio1 tio2 tio3 esd orientation mark v ddio v ssio v ssio v dd
56857 technical data, rev. 6 46 freescale semiconductor table 5-1 56857 pin identi fication by pin number pin no. signal name pin no. signal name pin no. signal name pin no. signal name 1miso 26 clko 51 rxd0 76 v dd 2mosi 27 rsto 52 txd0 77 tio3 3sck 28 reset 53 v ddio 78 tio2 4ss 29 hd3 54 v ssio 79 tio1 5v ddio 30 hd4 55 cs0 80 v ddio 6v ddio 31 hd5 56 cs1 81 tio0 7v ssio 32 hd6 57 cs2 82 v ssio 8v dd 33 hd7 58 cs3 83 hds 9v ss 34 v ddio 59 v dd 84 hcs 10 moda 35 v ssio 60 v dd 85 hreq 11 modb 36 v dd 61 v ss 86 hack 12 modc 37 v ss 62 ha0 87 v dd 13 v ddio 38 v ss 63 ha1 88 v ss 14 v ssio 39 de 64 ha2 89 v ssio 15 irqa 40 trst 65 hrwb 90 v ddio 16 irqb 41 tdo 66 std1 91 v ssio 17 v dda 42 tdi 67 srd1 92 std0 18 v ssa 43 tms 68 sck1 93 srd0 19 v ssa 44 tck 69 sc10 94 sck0 20 xtal 45 v ddio 70 sc11 95 sc00 21 extal 46 v ssio 71 sc12 96 sc01 22 hd0 47 v ddio 72 v ddio 97 sc02 23 hd1 48 v ddio 73 v ssio 98 v ddio 24 hd2 49 v ssio 74 rxd1 99 v ssio 25 v dd 50 v dd 75 txd1 100 v ssio
package and pin-out information 56857 56857 technical data, rev. 6 freescale semiconductor 47 figure 5-2 100-pin lqpf m echanical information please see www.freescale.com for the most current case outline. notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. datum plane -ab- is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums -t-, -u-, and -z- to be determined at datum plane -ab-. 5. dimensions s and v to be determined at seating plane -ac-. 6. dimensions a and b do not include mold protrusion. allowable protrusion is 0.250 (0.010) per side. dimensions a and b do include mold mismatch and are determined at datum plane -ab-. 7. dimension d does not include dambar protrusion. dambar protrusion shall not cause the d dimension to exceed 0.350 (0.014). dambar can not be located on the lower radius or the foot. minimum space between protrusion and an adjacent lead is 0.070 (0.003). 8. minimum solder plate thickness shall be 0.0076 (0.003). 9. exact shape of each corner may vary from depiction. ae ae ad seating (24x per side) r gauge plane detail ad section ae-ae s v b a 96x x e c k h w d f j n 9 dim min max min max inches millimeters a 13.950 14.050 0.549 0.553 b 13.950 14.050 0.549 0.553 c 1.400 1.600 0.055 0.063 d 0.170 0.270 0.007 0.011 e 1.350 1.450 0.053 0.057 f 0.170 0.230 0.007 0.009 g 0.500 bsc 0.020 bsc h 0.050 0.150 0.002 0.006 j 0.090 0.200 0.004 0.008 k 0.500 0.700 0.020 0.028 m 12 ref 12 ref n 0.090 0.160 0.004 0.006 q 1 5 1 5 r 0.150 0.250 0.006 0.010 s 15.950 16.050 0.628 0.632 v 15.950 16.050 0.628 0.632 w 0.200 ref 0.008 ref x 1.000 ref 0.039 ref -t- s t-u s 0.15 (0.006) z s ac s t-u s 0.15 (0.006) z s ac s t-u s 0.15 (0.006) z s ac -u- s t-u s 0.15 (0.006) z s ab -z- -ac- g plane -ab- s t-u m 0.20 (0.008) z s ac 0.100 (0.004) ac q m 0.25 (0.010)
56857 technical data, rev. 6 48 freescale semiconductor part 6 design considerations 6.1 thermal design considerations an estimation of the chip junction temperature, t j , in c can be obtained from the equation: equation 1: t j = t a + (p d x r ja ) where: t a = ambient temperature c r ja = package junction-to-ambie nt thermal resistance c/w p d = power dissipation in package historically, thermal resistance has been expressed as the sum of a j unction-to-case thermal resistance and a case-to-ambient thermal resistance: equation 2: r ja = r jc + r ca where: r ja = package junction-to-ambie nt thermal resistance c/w r jc = package junction-to-case thermal resistance c/w r ca = package case-to-ambient thermal resistance c/w r jc is device-related and ca nnot be influenced by the user. the user controls the thermal environment to change the case-to-ambien t thermal resistance, r ca . for example, the user ca n change the air flow around the device, add a heat sink, change the mounting ar rangement on the printed circuit board (pcb), or otherwise change the thermal diss ipation capability of the area su rrounding the device on the pcb. this model is most useful for ceramic pa ckages with heat sinks; some 90% of the heat flow is dissipated through the case to the heat sink and out to the ambient environment. for cera mic packages, in situations where the heat flow is split between a path to the case a nd an alternate path through the pcb, analysis of the device thermal performance may need the additional modeli ng capability of a sy stem level thermal simulation tool. the thermal performance of plastic packages is more dependent on the temperat ure of the pcb to which the package is mounted. again, if the estimations obtained from r ja do not satisfactorily answer whether the thermal performance is adequate, a sy stem level model may be appropriate. a complicating factor is the existe nce of three common definitions fo r determining the junction-to-case thermal resistance in plastic packages: ? measure the thermal resistance from the junction to th e outside surface of the package (case) closest to the chip mounting area when that surface has a proper heat sink. this is done to minimize temperature variation across the surface. ? measure the thermal resistance from the junction to where the leads are attached to the case. this definition is approximately equal to a junc tion to board thermal resistance. ? use the value obtained by the equation (t j ? t t )/p d where t t is the temperature of the package case determined by a thermocouple.
electrical design considerations 56857 technical data, rev. 6 freescale semiconductor 49 as noted above, the junction- to-case thermal resistances quoted in this data sheet are determined using the first definition. from a pr actical standpoint, that va lue is also suitable for determining the junction temperature from a case thermocoupl e reading in forced convection e nvironments. in natural convection, using the junction-to-case thermal resistance to estimate junction temperature from a thermocouple reading on the case of the package w ill estimate a junction temperature slightly hotter than actual. hence, the new thermal metric, thermal characterization parameter, or jt , has been defined to be (t j ? t t )/p d . this value gives a better estimate of the junction temperature in natura l convection when using the surface temperature of the package. remember that surfac e temperature readings of packages are subject to significant errors caused by inadequate attachment of the sensor to the surface and to errors caused by heat loss to the sensor. the recommended technique is to attach a 40-gauge thermocouple wire and bead to the top center of the package with thermally conductive epoxy. 6.2 electrical design considerations use the following list of considerat ions to assure correct operation: ? provide a low-impedance path from the board power supply to each v dd pin on the controller, and from the board ground to each v ss (gnd) pin. ? the minimum bypass requirement is to place six 0.01?0.1 f capacitors positioned as close as possible to the package supply pins. the recomm ended bypass configuration is to place one bypass capacitor on each of the ten v dd /v ss pairs, including v dda /v ssa. ? ensure that capacitor leads and associated prin ted circuit traces that connect to the chip v dd and v ss (gnd) pins are less than 0.5 inch per capacitor lead. ? use at least a four-layer printed circui t board (pcb) with two inner layers for v dd and gnd. ? bypass the v dd and gnd layers of the pcb with approximately 100 f, preferably with a high-grade capacitor such as a tantalum capacitor. ? because the device?s output signals have fast rise and fall times, pcb trace lengths should be minimal. ? consider all device loads as well as parasitic capacitance due to pcb traces when calculating capacitance. this is especially critical in system s with higher capacitive loads that co uld create higher transient currents in the v dd and gnd circuits. ? all inputs must be terminated (i.e., no t allowed to float) using cmos levels. caution this device contains protective circuitry to guard against damage due to high static voltage or electrical fields. however, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level.
56857 technical data, rev. 6 50 freescale semiconductor ? take special care to minimize noise levels on the v dda and v ssa pins. ? when using wired-or mode on the spi or the irqx pins, the user must provide an external pull-up device. ? designs that utilize the trst pin for jtag port or enhance on ce module functio nality (such as development or debugging systems) should allow a means to assert trst whenever reset is asserted, as well as a means to assert trst independently of reset . designs that do not require debugging functionality, such as consumer produc ts, should tie these pins together. ? the internal por (power on reset) w ill reset the part at power on with reset asserted or pulled high but requires that trst be asserted at power on.
electrical design considerations 56857 technical data, rev. 6 freescale semiconductor 51 part 7 ordering information table 7-1 lists the pertinent information needed to pl ace an order. consult a freescale semiconductor sales office or authorized di stributor to determine availability and to order parts. *this package is rohs compliant. table 7-1 56857 or dering information part supply voltage package type pin count frequency (mhz) order number DSP56857 1.8v, 3.3v low-profile quad flat pack (lqfp) 100 120 DSP56857bu120 DSP56857 1.8v, 3.3v low-profile quad flat pack (lqfp) 100 120 DSP56857bue *
56857 technical data, rev. 6 52 freescale semiconductor
how to reach us: home page: www.freescale.com e-mail: support@freescale.com usa/europe or locations not listed: freescale semiconductor technical information center, ch370 1300 n. alma school road chandler, arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) support@freescale.com japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064, japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. this product incorporates superflash? technology licensed from sst. ? freescale semiconductor, inc. 2005. all rights reserved. DSP56857 rev. 6 01/2007 information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical ex perts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part.

▲Up To Search▲

Price & Availability of DSP56857

	To Download DSP56857 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .